1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory, particularly, a semiconductor nonvolatile memory in which writing and erasing can be electrically carried out (an electrically erasable and programmable read only memory referred to as EEPROM, hereinafter). The invention is also relates to a semiconductor device.
2. Description of the Related Art
An electrically erasable and programmable nonvolatile memory (EEPROM) is known as a memory representing semiconductor nonvolatile memories. An EEPROM is a nonvolatile memory and different from a DRAM (dynamic random access memory) and an SRAM (static RAM), which represent other semiconductor memories. Therefore, data in the EEPROM would not be lost even when a power source turns off. Further, the EEPROM has a characteristic superior in integration density, ballistic resistance, consumption power, and writing/reading speed, compared with a magnetic disc representing the nonvolatile memories other than the above EEPROM. Due to such characteristic, a trend using an EEPROM as a substitute for various memories such as a magnetic disc and a DRAM has been increased, and further development in future is expected.
Information (storing information) in an EEPROM can be written and erased by charge injection to or drawing from a floating gate of each memory transistor. The storing information is discriminated by means of a threshold voltage corresponding to the amount of electric charges accumulated in the floating gate. Thus, it is important to control the threshold voltage after writing or erasing in order to accurately read out storing information of an EEPROM. To inject an electron to the floating gate of a memory transistor so as to increase the threshold voltage is referred to as writing in this specification. On the other hand, to draw an electron from the floating gate of a memory transistor so as to reduce the threshold voltage is referred to as erasing.
In each memory transistor constituting an EEPROM, a threshold voltage thereof is respectively different after writing or erasing even when writing or erasing is carried out at a same applied voltage for a same time period. This is because the speed of each memory transistor in writing or erasing is respectively different. When the threshold voltage after writing or erasing is not within at predetermined range, wrong information is to be read out.
FIG. 2A shows a relation between the writing time and the threshold voltage when writing is carried out in a memory transistor. FIG. 2A also shows a memory transistor A in which writing speed is fast and a memory transistor B in which writing speed is slow. A threshold voltage after writing is distributed in the vicinity of a predetermined threshold voltage Vth when the writing time is set at t0. Thus, a reading-out voltage should be selected in view of dispersion width of a threshold voltage D0 in order to accurately read out information of a memory transistor.
A range for selecting a reading-out voltage is narrow when the dispersion width of a threshold voltage after writing or erasing is large. It is necessary to widen a space between threshold voltages in respective storing conditions in order to accurately read out information, which leads increase of a writing time or an erasing time. Further, consumption power is also increased in writing or erasing. This is a further serious problem in a multi-value memory transistor in which three or more values of information are stored. Therefore, there has been an idea to decrease the dispersion width of a threshold voltage after writing or erasing.
For example, manufacturing processes is improved to manufacture a memory transistor having a uniform characteristic so that the dispersion width of a threshold voltage after writing or erasing can be decreased. This corresponds to make a difference small in writing speed between the memory transistor A in which a writing speed is fast and the memory transistor B in which a writing speed is slow, as shown in FIG. 2B. The threshold voltage after writing is distributed in the vicinity of a predetermined threshold voltage Vth when the writing time is set at t1. Dispersion width D1 of the threshold voltage after writing in this case is smaller than dispersion width D0 shown in FIG. 2A. In order to make a characteristic of a memory transistor uniform, there are so many points for improving the manufacturing processes that there is a limit in making the dispersion width of the threshold voltage small only by improving the manufacturing processes.
In the case that a method for driving a circuit is devised to compensate a writing time or an erasing time at the same time as the improvement of the manufacturing processes, the dispersion width of the threshold voltage after writing or erasing can be further made small. In this method, the threshold voltage of a memory transistor is checked point by point to carry out writing or erasing, which is continued until the threshold voltage reaches a value within a predetermined range. This method is called verify-writing or verify-erasing.
FIG. 2C shows a relation between the writing time and the threshold voltage in performing the verify-writing. The writing speed of the memory transistor A in which the writing speed is fast and that of the memory transistor B in which the writing speed is slow are respectively same as those of FIG. 2B. A period for a writing operation, which is denoted by W, and a period for a reading-out operation and judgment of a threshold voltage, which is denoted by V, are alternately repeated. The writing operation is not performed when a read-out threshold voltage exceeds the predetermined threshold voltage Vth. The memory transistor A and the memory transistor B complete writing respectively at a writing time t2A and t2B. In this case, dispersion width D2 of a threshold voltage after writing can be made smaller than D1. There is, however, a disadvantage that the writing time increases due to a reading-out operation and judgment of a threshold voltage.
In view of the above, a purpose of the invention is to provide a memory transistor in which writing or erasing can be carried out at a high speed with low consumption power and which is superior in controlling a threshold voltage after writing or erasing.
According to the invention, in a memory transistor having a characteristic that a part of a channel region (a channel forming region) turns off when the amount of electric charges accumulated in a floating gate reaches a specific value, writing or erasing at a high speed with low consumption power is self-concluded. The dispersion width of a threshold voltage is accordingly made narrow after writing or erasing.
In the invention, a channel region of a memory transistor is divided into two: a writing control region (a first region); and a writing region (a second region). The writing control region and the writing region are different in threshold voltage. Charge injection to a floating gate in a writing operation is only carried out in the writing region. The writing control region turns off when the amount of electric charges accumulated in the floating gate reaches a specific value in accordance with the charge injection. This characteristic can be used as a switch in a writing operation so that writing would be automatically stopped.
FIG. 3C shows a relation between the writing time and the threshold voltage (writing region) in the case of writing in a memory transistor according to the invention. FIG. 3A and FIG. 3B show a relation same as that of FIG. 2B and FIG. 2C, respectively, in the cases of writing and verify-writing in a certain time period described in paragraphs of the related art. In FIG. 3C, the writing speed of the a memory transistor A in which the writing speed is fast and that of a memory transistor B in which the writing speed is slow are respectively same as those of FIG. 3A and FIG. 3B. In FIG. 3C, writing automatically stops when a threshold voltage in the writing region reaches the predetermined threshold voltage Vth. The memory transistors A and B complete writing at the writing times t3A and t3B, respectively.
As shown in FIG. 3C, in a memory transistor according to the invention, dispersion width D3 of a threshold voltage after writing is almost equal to dispersion width of a difference in threshold voltage between the writing control region and the writing region, and therefore, does not depend on a difference in the writing speed of respective memory transistors. Thus, the dispersion width D3 of a threshold voltage after writing can be made smaller than the dispersion width D1 of a threshold voltage after writing for a certain time period shown in FIG. 3A. Furthermore, writing in a memory transistor according to the invention is superior to the verify-writing in consumption power and writing time since it is not necessary to carry out a reading-out operation and judgment of a threshold voltage.
The invention provides a semiconductor device provided with a plurality of memory transistors comprising:
a semiconductor comprising a source region, a drain region and a channel forming region;
a first insulating film formed on the semiconductor;
a floating gate formed on the first insulating film;
a second insulating film formed on the floating gate; and
a control rate formed on the second insulating film.
The semiconductor device comprising:
a first and a second regions in the channel forming region, and
means for intercepting charge injection from the first region to the floating gate (referred to as a first means, hereinafter);
means for carrying out charge injection from the second region to the floating gate (referred to as a second means, hereinafter); and
means for stopping charge injection from the second region to the floating gate (referred to as a third means, hereinafter).
Furthermore, the semiconductor device comprising:
a first and a second regions in the channel forming region, and
means for intercepting charge drawing from the floating gate to the first region (referred to as a fourth means, hereinafter);
means for carrying out charge drawing from the floating gate to the second region (referred to as a fifth means, hereinafter); and
means for stopping charge drawing from the floating gate to the second region (referred to as a sixth means, hereinafter).
The first and third means and the fourth and the sixth means correspond to a piled layer comprising the first region included in the channel forming region, the first insulating film formed on the first region, the floating gate formed on the first insulating film, the second insulation film formed on the floating gate and the control gate formed on the second insulating film. They also correspond to voltages applied to the source region, the drain region and the control gate as well as the amount of electric charges held in the floating gate.
The second and the fifth means correspond to a piled layer comprising the second region included in the channel forming region, the first insulating film formed on the second region, the floating gate formed on the first insulating film, the second insulating film formed on the floating gate and the control gate formed on the second insulating film. They also correspond to voltages applied to the source region, the drain region and the control gate as well as the amount of electric charges held in the floating gate.
The invention provides a semiconductor device provided with a plurality of memory cells to which first and second memory transistors are connected in series, the memory transistors respectively comprising:
a semiconductor comprising a source region, a drain region and a channel forming region;
a first insulating film formed on the semiconductor;
a floating gate formed on the first insulating film;
a second insulating film formed on the floating gate; and
a control gate formed on the second insulating film,
wherein the floating gates of the first and second memory transistors are connected respectively, and
wherein the control gates of the first and second memory transistors are connected respectively.
The above semiconductor device comprising:
means for intercepting charge injection from the channel forming region of the first memory transistor to the floating gate (referred to as a seventh means, hereinafter);
means for carrying out charge injection from the channel forming region of the first memory transistor to the floating gate (referred to as an eighth means, hereinafter); and
means for stopping charge injection from the channel forming region of the second memory transistor to the floating gate (referred to as a ninth means, hereinafter).
Furthermore, the semiconductor device comprising:
means for intercepting charge drawing from the floating gate to the channel forming region of the first memory transistor (referred to as a tenth means, hereinafter);
means for carrying out charge drawing from the floating gate to the channel forming region of the second memory transistor (referred to as an eleventh means, hereinafter); and
means for stopping charge drawing from the floating gate to the channel forming region of the second memory transistor (referred to as a twelfth means, hereinafter).
The seventh and ninth means and the tenth and the twelfth means correspond to a piled layer comprising the channel forming region of the first memory transistor, the first insulating film formed on the channel forming region, the floating gate formed on the first insulating film, the second insulation film formed on the floating gate and the control gate formed on the second insulating film. They also correspond to voltages applied to the source region, the drain region and the control gate of the first memory transistor as well as the amount of electric charges held in the floating gate of the first memory transistor.
The eighth and the eleventh means correspond to a piled layer comprising the channel forming region of the second memory transistor, the first insulating film formed on the channel forming region, the floating gate formed on the first insulating film, the second insulating film formed on the floating gate and the control gate formed on the second insulating film. They also correspond to voltages applied to the source region, the drain region and the control gate of the second memory transistor as well as the amount of electric charges held in the floating gate of the second memory transistor.